The present invention relates to a non-volatile memory semiconductor device and, in particular, to a technique effective when applied to a non-volatile memory semiconductor device including a memory cell in which a memory gate electrode is formed on the sidewall of a control gate electrode via an insulating film.
In Japanese patent laid-open No. 2006-49737 (patent document 1), a technique is described, which improves manufacturing yield as well as improving the performance of a semiconductor device. Specifically, a plurality of memory cells is arranged in an array and a selection gate electrode of the memory cell arranged side by side in a first direction (x direction) is connected by a selection gate line and a memory gate electrode is connected by a memory gate line. The memory gate lines respectively connected with the memory gate electrodes of the adjoining memory cells via a source region are not electrically connected with each other. The selection gate line has a first part extending in the first direction (x direction) and a second part having one end connected with the first part and extending in a second direction (y direction). The memory gate line is formed on the sidewall of the selection gate line via an insulating film and has a contact part extending in the first direction (x direction) from over the second part of the selection gate line to over an element isolation region, and is connected with a wire via a plug to fill a contact hole formed over the contact part.
In Japanese patent laid-open No. 2006-54292 (patent document 2), a technique is described, which is capable of making an attempt to reduce the manufacturing time and the cost by reducing the number of additional masks necessary to mount a nonvolatile memory mixedly in a standard CMOS logic process. Specifically, a sidewall structure is utilized and in a memory cell of split gate type in which a gate electrode has been silicidized, a standalone auxiliary pattern is arranged adjoining a selection gate electrode. A gap between the both is filled with polysilicon of a sidewall gate to form a wire part in a self-alignment manner, and a contact is provided to the wire part. The contact may overlap the auxiliary pattern and an element isolation region and it is possible to optimize its design while taking into consideration an occupied area.
In Japanese patent laid-open No. 2007-189063 (patent document 3), a technique is described, which provides a memory semiconductor device capable of making an attempt to extend a process margin and its manufacturing method. Specifically, on a polysilicon film constituting a memory gate wire etc., a part is formed, which extends from a part located on one of side surfaces of a control gate wire to the opposite side of a side on which the control gate wire is located and the part is used as a pad part. A contact hole is formed so as to expose the pad part. The height of the part of the polysilicon film located on one of the side surfaces of the control gate wire is set not more than the height of the control gate wire and the polysilicon film constituting the memory gate wire etc. does not overlap the control gate wire in a planar manner.